FIG. 1 shows a circuit diagram of a phase change memory cell 100 including a variable resistor 102 and a field effect transistor M1, as known in the prior art. The variable resistor 102 has one terminal coupled to a bit-line of a phase change memory device. The variable resistor 102 has another terminal coupled to a drain of the field effect transistor M1. The gate of the field effect transistor M1 is coupled to a word-line of the phase change memory device. The source of the field effect transistor M1 is coupled to a ground node.
FIG. 2 shows an isometric view of the structure for the variable resistor 102 formed with a phase change material 104. The variable resistor 102 includes a bottom electrode 106 formed below the phase change material 104, and includes a top electrode 108 formed above the phase change material 104.
The phase change material 104 is comprised of a chalcogenide material such as Ge—Sb—Te (GST) or Ge—Bi—Te (GBT) for example. Generally, a chalcogenide alloy contains at least one element from column V or VI of the Periodic Table of the Elements. The bottom electrode 106 is comprised of a high resistivity material such as TiAlN or TiN for example. The top electrode is comprised of a conductive material such as W, Ti, TiN, Ta, or TaN for example.
The resistance of the variable resistor 102 is determined by a structural phase of a programmable volume 110 of the phase change material 104. The programmable volume 110 is set to one of an amorphous phase or a crystalline phase from heating by a current flowing through the variable resistor 102. Such current flows through the bottom electrode 106, the phase change material 104, and the top electrode 108 of the variable resistor 102 for heating the programmable volume 110.
FIG. 3 shows a first temperature characteristic 112 (shown in dashed lines in FIG. 3) of the programmable volume 110 that is set to the amorphous phase for higher resistance. In that case, the programmable volume 110 is heated from time point t1 to time point t2 for attaining a temperature (such as 620° Celsius) higher than a melting temperature (Tm=610° Celsius) of the phase change material 104.
Subsequently, the programmable volume 110 is cooled relatively quickly back to room temperature from time point t2 to time point t3. FIG. 4 shows a first current characteristic 114 resulting in the first temperature characteristic 112 of FIG. 3. In that case, a relatively high level of current (such as 1.2 milli-Amps) flows through the variable resistor 102 from time point t1 to time point t2 (such as a duration in a range of 4 to 5 nano-seconds).
FIG. 3 also shows a second temperature characteristic 116 of the programmable volume 110 that is set to the crystalline phase for lower resistance. In that case, the programmable volume 110 is heated from time point t1 to time point t4 for attaining a temperature (such as 460° Celsius) that is slightly higher than a crystallization temperature (Tc=450° Celsius) of the phase change material 104.
Subsequently, the programmable volume 110 is cooled back to room temperature from time point t4 to time point t5. FIG. 4 shows a second current characteristic 118 resulting in the second temperature characteristic 116 of FIG. 3. In that case, a lower level of current (such as 0.56 milli-Amps) flows through the variable resistor 102 from time point t1 to time point t4 (such as a duration of about 500 nano-seconds).
The amorphous phase or the crystalline phase of the programmable volume 110 represents the binary states of the phase change memory cell 100.
FIGS. 5A, 5B, and 5C illustrate cross-sectional views during fabrication of the variable resistor 102 on a semiconductor substrate 120 according to the prior art. Referring to FIG. 5A, the bottom electrode 106 is formed as a plug on an inter-level material 124 which may be an insulator material. Spacers 126 surround the plug 106, and an insulating layer 128 surrounds the spacers 126. A phase change material 130 is deposited onto the plug 106, and a top electrode material 132 is deposited on the phase change material 130. In addition, a hard-mask 134 is patterned over the top electrode material 132.
Referring to FIG. 5B, exposed regions of the top electrode material 132 are etched away to form the top electrode 108. Referring to FIG. 5C, exposed regions of the phase change material 130 are etched away to form the phase change material structure 104 of FIG. 2.
In the prior art, such as disclosed in U.S. Patent Application Publication No. 2005/0227035 to Fuchioka et al., an etchant including a highly reactive halogen element such as chlorine and/or fluorine is used for etching the top electrode material 132 to form the top electrode 108. However, referring to FIG. 6, such a highly reactive halogen element also etches away the phase change material 130 to result in undercuts 140 into the phase change material 130.
In addition, halogen by-products 142 comprised of TiCl2, TiCl3, and/or TiCl4 are formed during such etching of the top electrode material 132. These halogen by-products 142 are difficult to remove by ashing and strip processes. Such remaining halogen by-products 142 may later diffuse into semiconductor structures during subsequent heating processes. Such diffusion may degrade integrated circuit performance, and such diffusion imposes a heat budget for minimizing such diffusion during subsequent heating processes.
Furthermore, the highly reactive halogen element used for etching the top electrode material 132 may react with the phase change material 130 alter the composition of the remaining phase change material structure 104.
Thus, a phase change memory device is desired to be fabricated without such disadvantageous features of the prior art.